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罗小蓉

Personal Information:

Gender:Female

Education Level:With Certificate of Graduation for Doctorate Study

Alma Mater:电子科技大学

Degree:Doctoral Degree

Status:On the job

School/Department:党委教师工作部、人力资源部

Administrative Position:主任

Business Address:电子科技大学清水河校区主楼B2 503

E-Mail:

Academic Honor: 新世纪优秀人才计划

Honors and Titles:

Profile

    2001年7月-至今 电子科技大学工作,期间2009-2010在剑桥大学进行博士后研究工作; 2011年聘为博士生导师,2012年破格晋升教授。 主持国 防卓越青年科技基金、国家自然科学基金、国家科技重大专项和重点研发计划以及省部级项目等30余项。发表SCI检索90余篇,其中以第一作者和通讯作者在微电子器件顶级期刊IEEE EDL和IEEE TED上发表论文30余篇,H指数为22,在重要国际学术会议做 5 次主题/特邀报告。作为第一发明人申请专利90余项,其中授权美国发明专利6项、中国发明专利44项。 


学术活动与兼职: 

1、IEEE international symposium on power semiconductor devices & ICs 的Technical programe Committee (TPC)委员(ISPSD是全球功率半导体领域最高级别专业学术会议);
2、IEEE EDS Power Devices and ICs,全球15名Technical Committee委员之一;
3、Advances in Material and Physics of Power Semiconductor and Integration,Guest Editor;
4、NMCI国际会议,大会Co-chair; 
5、担任国际权威期刊IEEE EDL,IEEE TED, IEEE Power Electronics Lett.,IEEE Tran. Power Electronics, Solid-State Electronics以及Microelectronics Journal等国际期刊的审稿人;
6、国家自然科学基金通讯评审专家;
7、国际会议IEEE ICSICT分会主席;
8、四川省电力电子节能技术与装备重点实验室学术委员会委员;
9、四川省电力电子学会学术委员会副主任。


荣誉和奖励(科技类): 2018年,国防卓越青年科技基金获得者;2018年,四川省有突出贡献的优秀专家;2017年,中国电子学会优秀科技工作者;2016年,四川省科技进步一等奖;2010年,国家科技进步二等奖; 2011年,教育部新世纪优秀人才支持计划; 2014年,教育部自然科学奖二等奖; 2013年,四川省青年科技奖; 2013年,四川省学术技术带头人后备人选; 2011年,四川省优秀博士学位论文 2012年,电子科技大学“百人计划”


科研项目:   

研究方向:功率半导体器件与集成电路

代表性项目:

1、军委GF科技卓越青年科学基金:批准号:2018-JCJQ-ZQ-060,负责人;

2、军委装发十三五预研:批准号,31513030201-2,负责人;

3、总装备部十二五预研:批准号,51308020304,负责人;

4、国家自然科学基金:空穴气增强型高压 GaN HEMT 机理与新结构研究,批准号:51677021,负责人;

5、国家自然科学基金:对称极化掺杂增强型功率 GaN HFET 机理与工艺实现研究,批准号:61874149,负责人;

6、国家自然科学基金:高压、超低功耗的易集成SOI横向功率MOSFET机理与新结构研究,批准号:61176069,负责人;

7、国家自然科学基金:新型低k介质埋层SOI器件耐压理论与新结构,批准号:60976060,负责人。

8、国家自然科学基金:结型场板横向功率器件机理与新结构研究,批准号:61376079,负责人;

9、国防科工局基础科研重点项目,批准号:JCKY2016210B008,子课题负责人;

10、教育部新世纪优秀人才支持计划:高k介质超结DMOS研究,批准号:NCET-11-0062,负责人;

11、国家科技重大专项:批准号:2014ZX02306001-002,主研;

12、国家科技重大专项:批准号:2013ZX02501002-003,主持。

13、装备部项目:XXXXX集成关键技术,批准号:51308020304,负责人;


热烈欢迎对以上研究方向有兴趣的同学加入本课题组进行硕士研究生、博士研究生和博士后科研工作。 

 

发表文章:   代表性学术成果(部分):

(一)学术论文  

[1] Xiaorong Luo*, Bo Zhang, Zhaoji Li, et al. A Novel 700-V SOI LDMOS With Double-Sided Trench [J]. IEEE ELECTRON DEVICE LETTERS, 2007, 28(5): 422-424

[2] Xiaorong Luo*, Bo Zhang, and Zhaoji Li. New High-Voltage (> 1200 V) MOSFET With the Charge Trenches on Partial SOI[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55(7): 1756-1761

[3] Xiaorong Luo*, Zhaoji Li, Bo Zhang, et al. Realization of High Voltage (> 700 V) in New SOI Devices With a Compound Buried Layer[J]. IEEE ELECTRON DEVICE LETTERS, 2008, 29(12):1-3

[4] Bo Zhang, Zhaoji Li, Shengdong Hu, et al. Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56(10): 2327-2334

[5] Xiaorong Luo*, Daping Fu, Lei Lei, et al. Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device Structure[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56(8): 1659-1666

[6] Xiaorong Luo*, Tianfei Lei, Yuangang Wang, et al. A High-Voltage LDMOS Compatible With High-Voltage Integrated Circuits on p-Type SOI Layer[J]. IEEE ELECTRON DEVICE LETTERS, 2009, 30(10): 1093-1095

[7] Xiaorong Luo*, Florin Udrea, Yuangang Wang, et al. Partial SOI Power LDMOS With a Variable Low-k Dielectric Buried Layer and a Buried P Layer[J]. IEEE ELECTRON DEVICE LETTERS, 2010, 31(6): 594-596

[8] Xiaorong Luo*, Bo Zhang, Tianfei Lei, et al.  Numerical and Experimental Investigation on a Novel High-Voltage ( >600-V) SOI LDMOS in a Self-Isolation HVIC[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57(11): 3033-3034

[9] Xiaorong Luo*, Yuangang Wang, Hao Deng, et al. Novel Low-k Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57(2): 535-538

[10] Xiaorong Luo*,Jie Fan, Yuangang Wang, et al. Ultralow Specific On-Resistance High-Voltage SOI Lateral MOSFET[J]. IEEE ELECTRON DEVICE LETTERS, 2011, 32(2): 185-187

[11] Xiaorong Luo*, T. F. Lei, Y. G. Wang, et al. Low On-Resistance SOI Dual Trench- Gates MOSFET[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59(2): 504-509

[12] Xiaorong Luo*, Y. H. Jiang, K. Zhou, et al. Ultralow Specific On-Resistance Superjunction Vertical DMOS with High-K Dielectric Pillar[J]. IEEE ELECTRON DEVICE LETTERS, 2012, 33(7): 1042-1044

[13] Xiao Rong Luo*, Jin Yong Cai, Ye Fan, et al. Novel Low-Resistance Current Path UMOS With High-K Dielectric Pillars[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 60(9): 2840-2846

[14] Kun Zhou, Xiaorong Luo*, Qing Xu, et al.A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific ON-Resistance[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014,61(7):2466-2472

[15] Xiaorong Luo*, Jie Wei, Xianlong Shi, et al. Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61(12): 4304-4308

[16] Kun Zhou, Xiaorong Luo*, Zhaoji Li, et al. Analytical Model and New Structure of the Variable-k Dielectric Trench LDMOS With Improved Breakdown Voltage and Specific ON-Resistance[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62(10): 3334-3340

[17] Xiaorong Luo*,  Qiao Tan, Jie Wei. Ultralow ON -Resistance High-Voltage p-Channel LDMOS With an Accumulation-Effect Extended Gate[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63(6): 2614-2619

[18] Kun Zhou, Xiaorong Luo*, Linhua Huang, et al. An Ultralow Loss Superjunction Reverse Blocking Insulated-Gate Bipolar Transistor With Shorted-Collector Trench[J]. IEEE ELECTRON DEVICE LETTERS, 2016, 37(11): 1462-1465

[19] Jie Wei, Xiaorong Luo*,Yanhui Zhang, et al. High-Voltage Thin-SOI LDMOS With Ultralow ON -Resistance and Even Temperature Characteristic[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63(4): 1637-1643  

[20] Xiaorong Luo*, Mengshan Lv, Chao Yin, et al. Ultralow ON-Resistance SOI LDMOS With Three Separated Gates and High-k Dielectric[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63(9): 3804-3807

[21] Xiaorong Luo*, Da Ma, Qiao Tan, et al. A Split Gate Power FINFET With Improved ON-Resistance and Switching Performance[J]. IEEE ELECTRON DEVICE LETTERS, 2016, 37(9): 1185-1188 

[22] Linhua Huang, Xiaorong Luo*, Jie Wei, et al. A Snapback-Free Fast-Switching SOI LIGBT With Polysilicon Regulative Resistance and Trench Cathode[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64(9): 3961-3966

[23] Weiwei Ge, Xiaorong Luo*,Junfeng Wu, et al. Ultra-Low On-Resistance LDMOS With Multi-Plane Electron Accumulation Layers[J]. IEEE ELECTRON DEVICE LETTERS, 2017, 38(7): 910-913

[24] Tao Sun, Xiaorong Luo*, JieWei, et al. A Carrier Stored SOI LIGBT With Ultralow ON-State Voltage and High Current Capability[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65(8): 3365-3370 

[25] Xiao Rong Luo*, Zheyan Zhao, Linhua Huang, et al. A Snapback-Free Fast-Switching SOI LIGBT With an Embedded Self-Biased n-MOS[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65(8): 3572-3576

[26] Jie Wei, Xiaorong Luo*, Linhua Huang, et al. Simulation study of a novel snapback-free and low turn-off loss reverse conducting IGBT with controllable trench gate in the collector side[J]. IEEE ELECTRON DEVICE LETTERS, 2018, 39(2): 252-255

[27] Gaoqiang Deng, Xiao Rong Luo*, JieWei, et al. A Snapback-Free Reverse Conducting Insulated-Gate Bipolar Transistor With Discontinuous Field-Stop Layer[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65(5): 1856-1861

[28] X. R. Luo*, Q. Liu, J. Wei, et al. A high bidirectional blocking capability insulated-gate bipolar transistor with ultralow loss[J]. IEEE Transactions on Electron Devices, 2018, 65(10): 4729-4733

[29] C. Yang, X. R. Luo*, A. B. Zhang, S. Y. Deng, D. F. Ouyang, F. Peng, J. Wei*, et al. AlGaN/GaN MIS-HEMT with AlN interface protection layer and trench termination structure[J]. IEEE Transactions on Electron Devices, 2018, 65(11): 5203–5207

[30] J. Wei, X. R. Luo*, G. Q. Deng, et al. Ultra-fast and low turn-off loss lateral IEGT with a MOS-controlled shorted anode[J]. IEEE Transactions on Electron Devices, 2018, 66(1): 533–538

[31] Jie Wei ,Xiaorong Luo*, Gaoqiang Deng ,TaoSun , Chenxia Wang, Kunfeng Zhu, Wei Cui, Zhikuan Wang, Zhaoji Li,Member, IEEE, and Bo Zhang,Member, IEEE. Ultrafast and Low-Turn-OFFLoss Lateral IEGT With a MOS-Controlled Shorted Anode[J]. IEEE Transactions on Electron Devices, 2019, 66(1): 533-538.

[32] Yuxi Wei , Xiaorong Luo*, Senior Member, IEEE, Weiwei Ge, Zheyan Zhao, Zhen Ma, and Jie Wei , Student Member, IEEE. A Split Triple-Gate Power LDMOS With Improved Static-State and Switching Performance[J]. IEEE Transactions on Electron Devices, 2019, 66(6): 2669-2674.

[33] Xiaorong Luo*, Yang Yang , TaoSun ,JieWei , Diao Fan, Dongfa Ouyang, Gaoqiang Deng , Yonghui Yang , Bo Zhang, and Zhaoji Li. A Snapback-Free and Low-Loss Shorted-Anode SOI LIGBT With Self-Adaptive Resistance[J]. IEEE Transactions on Electron Devices, 2019, 66(3): 1390-1395.

[34] Gaoqiang Deng , Xiaorong Luo*, Senior Member, IEEE,TaoSun , Zheyan Zhao,Diao Fan, and Bo Zhang , Senior Member, IEEE. An Injection Enhanced LIGBT on Thin SOI Layer Compatible With CMOS Process[J]. IEEE Transactions on Electron Devices, 2019, 66(6): 2681-2685.

[35] Kun Zhou, Xiaorong Luo*, Qing Xu, et al. A RESURF-Enhanced P-Channel SOI LDMOS with Ultralow Specific On-ResistanceIEEE Tran. Electron Devices, 2014, 61(7)2466-2472. 其它国内外重要期刊(SCI收录) 

[36] Xiaorong Luo*, Wei Zhang, Zhaoji Li, et al. A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with step thickness drift region, Semiconductor Science and technology, 2008, 23 (3):No.035028. 

[37] Xiaorong Luo*, Bo Zhang, Zhaoji Li. A New Structure and its Analytical Model for the Electric Field and Breakdown Voltage of SOI High Voltage Device with Variable-k Dielectric Buried Layer, Solid-State Electronics, 2007,51:493-499. 

[38] Xiaorong Luo*, Bo Zhang, Zhaoji Li. A new SOI high voltage device with step thickness sustained voltage layer. Electronics Lett. 2008, 44 (1). 入选Electronics Letters大中华地区“精选特刊”,该特刊从大中华地区于2005-2008年期间在Electronics Letters发表的论文中精选 

[39] Luo Xiao-Rong*, Luo Yin-Chun, Fan Ye, et al., A low specific on-resistance SOI MOSFET with dual gates and a recessed drain, Chin. Phys. B, 22(2), 027304, 2013. 

[40]Luo Xiao-Rong*, Wang Qi, Yao Guo-Liang, A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitchChin. Phys. B, 22 (2), 027303, 2013. 

[41] Luo Xiao-Rong*, G L Yao, Y G Wang, et al, A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integrationChin. Phys. B, 21(2), 068501, 2012. 

[42] Luo Xiao-Rong*, Wang Yuan-Gang, Deng Hao, and Florin Udrea, A Novel Partial Silicon-On-Insulator High Voltage LDMOS with Low-k Dielectric Buried Layer, Chinese Physics B, 19(7), 077306-1-6, 2010. 

[43] Luo Xiao-Rong*, Yao Guo-liang, Wang Yuan-Gang, et al.Ultra-low On-Resistance High Voltage (>600) SOI MOSFET with a Reduced Cell Pitch, Chinese Physics B, 20(2): 028501, 2011. 

[44] Wang pei, Luo Xiao-Rong*, Ultra-low specific on-resistance vertical double-diffused metal oxide semiconductor with a high-k dielectric-filled extended trench, Chin. Phys. B, 22( 2), 027305, 2013. 

[45] Zhou Kun, Luo Xiao-Rong*, Fan Yuan-Hang et al, Low on-resistance buried current path SOI P-channel LDMOS compatible with N-channel LDMOS Chin. Phys. B, 067306, 2013. 

[46] Fan Yuan-Hang, Luo Xiao-Rong*,Wang Pei, Zhou Kun et al, A High Figure-of-Merit SOI MOSFET with a Double-Sided Charge Oxide-Trench, Chin. Phys. Lett, 30(8), 088503, 2013. 

[47] 王骁玮,罗小蓉*,尹超 等,高k介质电导增强SOI LDMOS机理与优化设计,物理学报,v62, n23. 

[48] Shi Xian-Long, Luo Xiao-Rong*, Wei Jie,et al. ,A novel LDMOS with a junction field plate and a partial N-buried layer, Chin. Phys. B Vol. 23, No. 12 (2014) 127303. 该论文在编辑部网站 Highlights”专栏(http://cpb.iphy.ac.cn/)并将在CPB国外合作发行商英国物理学会出版社(IOPP)网站的 "Featured Articles ”专栏(http://iopscience.iop.org/cpb/ )发表

[49] Luo Yin-Chun, Luo Xiao-Rong*, Hu Gang-Yi, et al. A low specific on-resistance SOI LDMOS with a novel junction field plate,Chin. Phys. B Vol. 23, No. 7 (2014) 077306. 

[50] Li Peng-Cheng, Luo Xiao-Rong*, Luo Yin-Chun, et al. An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer,Chin. Phys. B Vol. 24, No. 4 (2015) 047304. 

[51] WANG Zhuo, LI Peng-Cheng, ZHANG Bo, FAN Yuan-Hang, XU Qing, LUO Xiao-Rong*, Ultralow Specific on-Resistance Trench MOSFET with a U-Shaped Extended Gate, CHIN. PHYS. LETT. Vol. 32, No. 6 (2015) 068501. 

[52] Wang Yuan-Gang, Luo Xiao-Rong*, Ge Rui, Wu Li-Juan, Chen Xi, Compound buried layer SOI high voltage device with step buried oxide, Chin. Phys. B, 077304, 2011. 功率半导体领域顶级国际会议IEEE ISPSD及邀请报告: 

[53] Jie Wei, Xiaorong Luo* , Yanhui Zhang, et al. Accumulation-Mode High Voltage SOI LDMOS with Ultralow Specific On-resistance, IEEE ISPSD, Hongkong, China, 9-14, May, 2015. 

[54]Xiaorong Luo*, Y G Wang, M Qiao, Bo Zhang, Zhaoji Li, et al. Novel High Voltage LDMOS on Partial SOI with double-sided Charge Trenches, IEEE ISPSD, San Diego, California, USA , 23-26 May, 2011. 

[55]Xiaorong Luo*, Tianfei Lei, Wang Yuangang, et al. A Novel High Voltage (>700V) SOI LDMOS with Buried N-layer in a Self-isolation High Voltage Integrated Circuit, IEEE ISPSD, Hiroshima, Japan, June 6, 2010. 

[56] Kun Zhou, Xiaorong Luo*, Qing Xu, et al. Ultralow Specific On-Resistance High Voltage LDMOS with a Varible-K Dielectric Trench, IEEE ISPSD, Waikoloai, USA, Jun. 2014. 

[57] Jie Wei, Xiaorong Luo*, Xianlong Shi, et al. An Improved On-resistance High Voltage LDMOS with Junction Field Plate, IEEE ISPSD, Waikoloai, USA, Jun. 2014. 

[58] Xiaorong Luo*Kun ZhouZhaoji LiBo Zhang Ultralow specific on-resistance trench lateral powe MOSFETS 2014 IEEE International Conference on Solid-State and Integrated Circuit Technology1784-17872014.10.28-2014.10.31。邀请报告。 

[59] Kun Zhou, Linhua Huang, Xiaorong Luo*, Zhaoji Li; Bo Zhang.Characterization and Performance Evaluation of the Superjunction RB-IGBT in Matrix Converter,IEEE Transactions on Power Electronics, DOI: 10.1109/TPEL.2017.2709323,2018.


(二)发明专利 6项美国授权专利 44项中国授权专利 

[1] Xiaorong Luo, Florin Udrea, SOI Lateral MOSFET Devices, US patent, 8,716,794 B2; 

[2] Xiaorong Luo, Guoliang Yao, Tianfei Lei, et al. Trench-type semiconductor power devices, US patent, 8,890,280 B2

[3] Xiaorong Luo, Jiayun Xiong,Chao Yang, et al.ENHANCEMENT MODE HIGH ELECTRON MOBILITY TRANSISTOR, US patent, 9,431,527 B1

[4] Xiaorong Luo, Weiwei Ge, Junfeng Wu, et al. A KIND OF POWER TRI-GATE LDMOS, US patent, 9,620,638 B1

[5] Xiaorong Luo, Gaoqiang Deng, Kun Zhou, et al. REVERSE CONDUCTING IGBT, US patent, 10,340,373 B2

[6] Xiaorong Luo, Fu Peng, Chao Yang, et al. POLARIZATION-DOPED ENHANCEMENT MODE HEMT, US patent, 10,304,931 B2

[7] 罗小蓉,姚国亮,雷天飞等,槽型半导体功率器件,专利号:ZL201010610944.2

[8] 罗小蓉,姚国亮,雷天飞等, SOI横向MOSFET器件和集成电路,专利号:ZL201110003586.3

[9] 罗小蓉,王元刚,姚国亮等,具有延伸沟槽的超结半导体器件的制造方法,专利号:ZL201110051878.4

[10] 罗小蓉,姚国亮,王元刚等,超结结构和超结半导体器件的制造方法,专利号:ZL201110051879.9

[11] 罗小蓉,王元刚,姚国亮等,一种槽型纵向半导体器件的制造方法,专利号:ZL201110075550.6

[12] 罗小蓉,姚国亮,王元刚等,一种具有高K介质槽的半导体功率器件,专利号:ZL201110075604.9

[13] 罗小蓉,周坤,姚国亮等,一种双栅功率MOSFET器件,专利号:ZL201210179867.9

[14] 罗小蓉,蒋永恒,蔡金勇等,槽栅半导体功率器件,专利号:ZL201210220695.5

[15] 罗小蓉,王沛,蔡金勇等, 一种槽型半导体功率器件的制造方法,专利号:ZL201210226462.6

[16] 罗小蓉,王沛,范叶等, 一种槽型半导体功率器件,专利号:ZL201210226454.1

[17] 罗小蓉,周坤,范叶等, 纵向功率半导体器件的制造方法,专利号:ZL201210306150.6

[18] 罗小蓉,罗尹春,周坤等, 一种SOI基PMOSFET功率器件,专利号:ZL201210441287.2

[19] 罗小蓉,罗尹春,范远航等, 一种具有结型场板的SOI功率LDMOS器件,专利号:ZL201310202568.7

[20] 罗小蓉,魏杰,罗尹春等, 一种具有结型场板的功率LDMOS器件,专利号:ZL201310202668.X

[21] 罗小蓉,王骁玮,范叶等, 一种横向SOI功率半导体器件,专利号:ZL201310346866.3

[22] 罗小蓉,田瑞超,徐菁等,具有U型延伸栅的SOI槽型LDMOS器件,专利号:ZL201410142967.3

[23] 罗小蓉,李鹏程,田瑞超等,一种槽型积累层MOSFET器件,专利号:ZL201410142500.9

[24] 罗小蓉,李鹏程,田瑞超等,一种槽型横向MOSFET器件的制造方法,专利号:ZL201410143064.7

[25] 罗小蓉,田瑞超,魏杰等, 一种横向SOI功率LDMOS器件,专利号:ZL201410439282.5

[26] 罗小蓉,熊佳云,杨超等, 一种用于GaN基HEMT器件的自适应偏置场板,专利号:ZL201410471520.0

[27] 罗小蓉,杨超,熊佳云等, 一种缓冲层荷电RESURF HEMT器件,专利号:ZL201410851598.5

[28] 罗小蓉,刘建平,张彦辉等, 一种横向MOSFET器件的制造方法,专利号:ZL201510410002.2

[29] 罗小蓉,张彦辉,刘建平等, 一种LDMOS器件的制造方法,专利号:ZL201510408917.X

[30] 罗小蓉,张彦辉,刘建平等,一种LDMOS器件的制造方法2,专利号:ZL201510410157.6

[31] 罗小蓉,熊佳云,杨超等,一种增强型HEMT器件,专利号:ZL201510456018.7

[32] 罗小蓉,杨超,熊佳云等,一种具有结型半导体层的HEMT器件,专利号:ZL201510456005.X

[33] 罗小蓉,尹超,谭桥等,一种功率MOS器件,专利号:ZL201510556581.1

[34] 罗小蓉,阮新亮,周坤等,一种短路阳极横向绝缘栅双极型晶体管,专利号:ZL201510936970.7

[35] 罗小蓉,阮新亮,周坤等,一种SA-LIGBT,专利号:ZL201510937715.4

[36] 罗小蓉,吕孟山,尹超等,一种槽栅功率MOSFET器件,专利号:ZL201610015326.0

[37] 罗小蓉,吕孟山,尹超等,一种具有三栅结构的HK SOI LDMOS器件,专利号:ZL201610333480.2

[38] 罗小蓉,邓高强,周坤等,一种横向IGBT,专利号:ZL201610344066.1

[39] 罗小蓉,杨超,吴俊峰等,一种积累型垂直HEMT器件,专利号:ZL201610432032.8

[40] 罗小蓉,黄琳华,周坤等,一种具有超结的RB-IGBT,专利号:ZL201610513921.7

[41] 罗小蓉,葛薇薇,吴俊峰等,一种三栅功率LDMOS,专利号:ZL201610554363.9

[42] 罗小蓉,邓高强,周坤等,一种逆导型IGBT(1),专利号:ZL201610786927.1

[43] 罗小蓉,邓高强,周坤等,一种逆导型IGBT(2),专利号:ZL201610786770.2

[44] 罗小蓉,黄琳华,邓高强等,一种具有双栅的RC-IGBT,专利号:ZL201610812713.7

[45] 罗小蓉,张凯,孙涛等,一种碳化硅VDMOS器件,专利号:ZL201710137017.5

[46] 罗小蓉,张波,李肇基等,一种具有窗口的双介质SOI耐压结构及其SOI功率器件,专利号:ZL200610022119.4

[47] 罗小蓉,张伟,詹瞻等,基于自隔离技术的介质场增强SOI耐压结构,专利号:ZL200910058145.6

[48] 罗小蓉,张伟,邓浩等,在厚膜SOI材料中形成图形化半导体埋层的方法,专利号:ZL200910058291.9

[49] 罗小蓉,黄磊,付达平等,双面介质槽部分SOI材料的制备方法,专利号:ZL200910058508.6

[50] 罗小蓉,弗罗林·乌德雷亚(外),SOI横向MOSFET器件,专利号:ZL201010173833.X

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Educational Experience

  • 1992.9-1996.6

    四川师范学院 | 物理 | Doctoral Degree | Bachelor's Degree
     

  • 1998.9-2001.6

    四川大学 | 凝聚态物理 | With Certificate of Graduation for Study as Master's Candidates | Master's Degree
     

  • 2002.9-2007.12

    电子科技大学 | 微电子学与固体电子学 | With Certificate of Graduation for Doctorate Study | Doctoral Degree
     

Work Experience

  • 2018.7-Now

     电子科技大学人力资源部教师发展中心  | 主任 
     

  • 2017.12-2018.6

     电子科技大学电子科学与技术学院(示范性微电子学院)  | 教师 
     

  • 2001.7-2017.11

     电子科技大学微电子与固体电子学院  | 教师 
     

  • 1996.7-1998.7

     四川省北川民族中学  | 中学教师 
     

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