Affilication of Author(s): 电子科技大学
Patent desc: 一种新型DRAM集成电路的结构，涉及集成电路技术和半导体技术。本发明是基于一种新型的纵向柱状TMOS器件结构,最下层为N+掺杂衬底和N‑外延层作为漏极，中间是P外延层作为栅极沟道，最上方是N+锗硅外延层作为源极。柱状结构的外圈被氧化层包围，其中三面覆盖多晶硅层作为栅极，剩下一面覆盖金属层与MOS管的漏极形成电容。多晶硅上有一个引线孔，接字线。锗硅层上是另一个引线孔，接位线。本发明所要解决的关键技术问题是：提供一种DRAM结构，提供一种新型DRAM集成电路的结构，实现器件的小面积、高电流密度、低导通电...
State of Patent: 授权
Authorization number: ZL201911306287.X
Service Invention or Not: no
Application Date: 2019-12-18
Authorization Date: 2022-12-06
Publication Date: 2020-02-21
Associate Professor
Supervisor of Master's Candidates
Gender : Male
Education Level : With Certificate of Graduation for Doctorate Study
Degree : Doctor of Engineering
Status : Professor
Date of Employment : 1999-07-01
Discipline:Microelectronics and Solid State Electronics
Email : 10049f2ecec39b2772b40bd0e537871cbdca7f4e3be4c542f66a58a33a971c30c504d9b05fe02e941ce4694a8b2d8a41e5c6b3c49467aba6cde4f1c39537e3fd98018c3f23962998d7aab91502db5e1fc216748b215e9adb26612190beeb2da4e64e2b62b522173ab5d81e13f0628c4c35db3bcb10594fee326300b0e55bb1d1
The Last Update Time : ..
