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    王成

    • 教授 博士生导师
    • 主要任职:电子科技大学
    • 性别:男
    • 学历:博士研究生毕业
    • 学位:哲学博士学位
    • 入职时间: 2021-02-20
    • 学科:电路与系统
    • 办公地点:清水河校区科研4号楼A区232房间
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    • 2022当选:国家优秀青年基金获得者

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    A 93.4–104.8-GHz 57-mW Fractional-N Cascaded PLL With True In-Phase Injection-Coupled QVCO in 65-nm CMOS Technology

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    所属单位:Massachusetts Institute of Technology (MIT)

    发表刊物:IEEE Transactions on Microwave Theory and Techniques (TMTT)

    刊物所在地:USA

    关键字:Cascaded phase-locked loop (PLL), CMOS voltage-controlled oscillator (VCO), frequency synthesizer

    摘要:A fully integrated 93.4-104.8-GHz 57-mW fractional-N cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional-N PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition range are achieved simultaneously. The transformer-based true in-phase injection coupled technique is adopted in the QVCO to obtain both low phase noise and low-power consumption. The proposed cascaded PLL was fabricated in a 65-nm CMOS technology with silicon size of 0.88 mm2.

    备注:https://ieeexplore.ieee.org/document/8686223

    全部作者:Guangyin Feng,Fanyi Meng,Cheng Wang,Chenyang Li,Kaituo Yang,Bei Liu,Chirn Chye Boon

    第一作者:Xiang Yi

    论文类型:期刊

    通讯作者:Zhipeng Liang

    论文编号:10.1109/TMTT.2019.2906614

    学科门类:工学

    一级学科:电子科学与技术

    卷号:67

    期号:6

    页面范围:2370-2381

    是否译文:

    发表时间:2019-06-01