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A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture

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Journal:Advances in Electrical and Computer Engineering

All the Authors:Y. Li,H. Li

First Author:J. Wang

Volume:12

Issue:4

Page Number:19-24

Translation or Not:no

Date of Publication:2012-11-18

Date of Publication:2012-11-18

Pre One:An Efficient Link Bandwidth Design Method for Application Specific Network-on-Chip

Next One:System-Level Buffer Allocation for Application Specific Network-on-Chip with Wormhole Routing

王坚

Gender:Male Education Level:With Certificate of Graduation for Doctorate Study Degree:Doctor of Engineering Status:Professor E-Mail:

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