Ruan Aiwu received her Ph.D degree from School of Electronics and Information Engineering, Northwestern Polytechnical University in1998. From 1999 to 2001, she performed research as Post-doctoral Fellow at MicroFabrication Lab, Division of Microelectronics, School of EEE, Nanyang Technologic University, Singapore. From 2001 to 2002, she was a Research Fellow with Wireless Position Systems Centre, Nanyang Technologic University, Singapore. From 2002 to 2004, she was a Senior Engineer with Advanced Technology Center, Singapore Technologoies Engineering. In March 2005, she joined the faculty of Microsystems and IC Design Center, School of Microelectronics and Solid-State Electronics, State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science & Technology of China as a Professor. Her current research interests are
● The third generation verification technology based SOC debugging
Increasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. The third generation verification technology, SOC HW/SW co-verification becomes one of the state-of-art verification methodologies. SOC HW/SW co-verification is defined as two different simulator coupled to each other to complete the simulation of a single design. This technology is characterized by two inherently conflicting issues: signal observability and simulation performance. A debugging methodology with both full observability and full acceleration is required to be studied.
● Defect and fault tolerant computing for FPGA applications
Field programmable gate arrays (FPGAs) provide programmable platforms for many applications such as net-working, signal processing, and fault-tolerant computing. The FPGAs are widely used for manufacturing complex digital systems due to the advantages they offer such as rapid hardware realization, reduce time to market and low development cost. As shrinking of transistors size, FPGAs become more vulnerable to defects during lifetime operation. The programmability and modularity of an FPGA are readily adaptable to fault tolerance. Defect and fault-tolerant computing based on FPGAs use self-repair techniques to avoid faulty resources after diagnosing them. The first step in self repair is to use periodic test or concurrent error detection (CED) to detect faults in run time. When faults are detected, the second step is to use diagnosis techniques to locate the faulty resources. The third step attempts to remap the design in the FPGA to bypass the faulty resources, such that the desired design can still function correctly.
● Reconfigurable computing for FPGA applications
A reconfigurable system is a system whose sub-systems and/or sub-system configurations can be changed or modified after fabrication to (better) serve a certain purpose. Reconfigurable computing designates computing based on computers whose processing units, memory units, communication channels and/or their composition can change function and/or (spatial) configuration after fabrication, prior or during the run-time of a particular set of applications, application, program or part of a program. The core component of a reconfigurable computing system is programmable hardware that can be temporarily (partly) customized/programmed to (better) serve a specific computation or set of computations.
● Hardware trojan design, implementation and detection for FPGAs

Outsourcing the design and fabrication of integrated circuits (ICs) has raised major concerns about their security and reliability. Realized by the intentiona