H. Huang, J. Cheng, B. Yi, W. Zhang, and W. T. Ng, “A unified model of vertical doped and polarized superjunction GaN devices.” Applied Physics Letters, vol. 116, 102103, Mar. 2020. (入选编辑精选Editor’s Pick).

H. Huang, Y. Xu, H. Li, Z. Zhang, Y. Li, H. Zhang, J. Cheng, B. Yi, Z. Wang, G. Zhang, “Optimization and comparison of specific on-resistance for superjunction MOSFETs considering three-dimensional and insulator-pillar concepts,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1162-1168, March 2022, doi: 10.1109/TED.2021.3130105.

H. Huang, K. Hu, W. Xu, S. Xu, W. Cui, W. Zhang, and W. T. Ng, “Numerical solutions for electric field lines and breakdown voltages in superjunction-like power devices,” IEEE Trans. Electron Devices, vol. 67, no. 9, 3898-3902, Sep. 2020.

H. Huang, S. Xu, W. Xu, K. Hu, J. Cheng, H. Hu, and B. Yi, “Optimization and comparison of drift region specific on-resistance for vertical power Hk MOSFETs and SJ MOSFETs with identical aspect ratio.” IEEE Trans. Electron Devices, vol. 67, no. 6, pp. 2463-2470, Jun. 2020.

H. Huang and X. Chen, “Optimization of specific on-resistance of semisuperjunction trench MOSFETs with charge balance,” IEEE Trans. electron devices, vol. 60, no. 3, pp. 1195–1201, 2013.

H. Huang and X. Chen, “Optimization of specific on-resistance of balanced symmetric superjunction MOSFETs based on a better approximation of ionization integral,” IEEE Trans. Electron Devices, vol. 59, no. 10, pp. 2742–2747, 2012

J. Xiong, H. Huang, W. Zhen, Z. Zhang, J. Cheng, B. Yi, H. Yang, G. Zhang, “A Rigorous Analysis of Specific ON-resistance for 4H-SiC Superjunction Devices,” ICSICT 2022, accepted.

X. Tong, H. Pei, W. Zhen, H. Huang, Z. Zhang, J. Cheng, B. Yi, and H. Yang, “A Novel Insulating-Pillar Superjunction with Vertical Insulators: Breakthrough of Specific ON-Resistance Limit,” ICSICT 2022, accepted.

J. Zhang, Y. Jiang, H. Huang, Z. Zhang, J. Cheng, B. Yi, H. Yang, and Z. Wang, “Superjunction SiC TCOX-MOSFET: Study and Comparison,” ICSICT 2022, accepted.

WenjunLi, Haimeng Huang, Zimin Zhang, Junji Cheng, Bo Yi, Hongqiang Yang, and Zhiming Wang， “Optimization of Specific ON-Resistance of Superjunction Device with Two-Zones Variation Vertical Doping Profile”, ICSICT 2022, accepted.

J. Huang, H. Huang*, and X. Chen, “Simulation study of a low on-state voltage superjunction IGBT with self-biased PMOS,” IEEE Trans. Electron Devices, vol. 66, no. 7, pp. 3242–3246, 2019.

J. Huang, H. Huang*, and X. Chen, “Simulation study of a low on-state voltage and saturation current TCIGBT with diodes,” IEEE Trans. Electron Devices, vol. 66, no. 3, pp. 1617–1620, 2019.

J. Huang, H. Huang*, X. Lyu, and X. B. Chen, “Simulation study of a low switching loss FD-IGBT with high di/dt and dv/dt controllability,” IEEE Trans. Electron Devices, vol. 65, no. 12, pp. 5545–5548, 2018.

J. Cheng, H. Huang, B. Yi, W. Zhang, and W. T. Ng, “A TCAD study on lateral power MOSFET with dual conduction paths and high-k passivation.” IEEE Electron Devices Letters, vol. 41, no. 2, pp. 260–263, 2020.

B. Yi, H. Hu, J. Lin, J. Cheng, H. Huang, and M. Kong, “SiC trench MOSFET with integrated side-wall Schottky barrier diode having p+ electric field shield,” IEICE Electronics Express, pp. 16–20 181 135, 2019.

W. Chen, J. Cheng, H. Huang, B. Zhang, and X. B. Chen, “The oppositely doped islands IGBT achieving ultralow turnoff loss,” IEEE Trans. Electron Devices, vol. 66, no. 8, pp. 3690–3693, 2019.

J. Lin, J. Cheng, P. Li, W. Chen, and H. Huang, “Study on SrTiO3 film for the application of power devices,” Superlattices and Microstructures, vol. 130, pp. 168–174, 2019.

J. Cheng, W. Chen, J. Lin, P. Li, B. Yi, H. Huang, and X. B. Chen, “Potential of utilizing high-k film to improve the cost performance of trench LDMOS,” IEEE Trans. Electron Devices, vol. 66, no. 7, pp. 3049–3054, 2019.

J. Wu, H. Huang, B. Yi, H. Hu, H. Hu, and X. B. Chen, “A snapback-free and low turn-off loss reverse-conducting SOI-LIGBT with embedded diode and MOSFET,” IEEE Journal of the Electron Devices Society, vol. 7, pp. 1013–1017, 2019.

B. Yi, M. Kong, J. Lin, J. Cheng, H. Huang, and X. Chen, “A 600-V super-junction pLDMOS utilizing electron current to enhance current capability,” IEEE Trans. Electron Devices, vol. 66, no. 5, pp. 2314–2320, 2019.

H. Hu, H. Huang, and X. B. Chen, “A novel double-RESURF SOI lateral TIGBT with self-biased nMOS for improved VCE-Eoff tradeoff relationship,” IEEE Trans. Electron Devices, vol. 66, no. 1, pp. 814–820, 2019.

H. Li, H. Huang, and X. Chen, “An improved SOI trench LDMOS with double vertical high-k insulator pillars,” Journal of Semiconductors, vol. 39, no. 9, p. 094009, 2018.

S. Guo, H. Huang, and X. B. Chen, “Study of the SOI-LDMOS with low conduction loss and less gate charge,” IEEE Trans. Electron Devices, vol. 65, no. 4, pp. 1645–1649, 2018.

P. Li, H. Huang, and X. Chen, “A low on-state voltage TIGBT with planar gate self-biased pMOS,” in 2017 IEEE 12th International Conference on Power Electronics and Drive Systems (PEDS). IEEE, 2017, pp. 456–459.

L. Liang, H. Huang, and X. Chen, “A variation lateral doping layer and lightly doped region compensated superjunction LDMOS,” in 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2016, pp. 120–123.

Z. Lin, H. Huang, and X. Chen, “An improved superjunction structure with variation vertical doping profile,” IEEE Trans. Electron Devices, vol. 62, no. 1, pp. 228–231, 2014.

H. Huang and X. Chen, “New expressions for non-punch-through and punch-through abrupt parallel-plane junctions based on Chynoweth law,” Journal of Semiconductors, vol. 34, no. 7, p. 074003, 2013.

H. Huang and X. Chen, “An analytical model of the electric field distributions of buried superjunction devices,” Journal of Semiconductors, vol. 34, no. 6, p. 064006, 2013.

H. Huang, Y. Wang, and X. Chen, “An analytical model for SOI triple RESURF devices,” in 2011 9th IEEE International Conference on ASIC. IEEE, 2011, pp. 547–550