Affilication of Author(s): 电子科技大学
Patent desc: 本发明公开了一种FinFET集成电路基本单元，涉及微电子技术和集成电路领域。该基本单元为多层结构，最下层为低掺杂阱区，该低掺杂阱区包括底层和在底层上脊状凸起；该脊状凸起两侧设置有隔离层，该隔离层上表面与低掺杂阱区脊状凸起的上表面齐平；顺着低掺杂阱区脊状凸起的上表面依次设置两侧面和上表面都齐平的：漏极半导体区、轻掺杂漏区、沟道半导体区、轻掺杂源区、源极半导体区；所述沟道半导体区的两侧面和上表面上设置有栅电极，并且该栅电极与沟道半导体区之间设置有一层栅介质层作为隔离。本发明包裹沟道区和N‑掺杂区的栅氧化层的介
Application Number: CN202111015860.9
Authorization number: CN113838911B
Service Invention or Not: no
Application Date: 2021-08-31
Authorization Date: 2023-03-21
Publication Date: 2021-12-24
Associate Professor
Supervisor of Master's Candidates
Gender : Male
Education Level : With Certificate of Graduation for Doctorate Study
Degree : Doctor of Engineering
Status : On the job
Date of Employment : 1999-07-01
Discipline:Microelectronics and Solid State Electronics
Email : 10049f2ecec39b2772b40bd0e537871cbdca7f4e3be4c542f66a58a33a971c30c504d9b05fe02e941ce4694a8b2d8a41e5c6b3c49467aba6cde4f1c39537e3fd98018c3f23962998d7aab91502db5e1fc216748b215e9adb26612190beeb2da4e64e2b62b522173ab5d81e13f0628c4c35db3bcb10594fee326300b0e55bb1d1
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