Publications

1. Pengfei Zhai, Zheng Zhu, Xiong Zhou, Yan Cai, Fan Zhang, Qiang Li, "An on-chip power-supply noise analyzer with compressed sensing and enhanced quantization," IEEE Journal of Solid-State Circuits (JSSC), Jan. 2022.
   

2. Sanfeng Zhang, Xiong Zhou, Chen Gao, Qiang Li, “A 130-dB CMRR instrumentation amplifier with common-mode replication,” IEEE Journal of Solid-State Circuits (JSSC), Jan. 2022.

3. Xin Si, Y.-N. Tu, W.-H. Huang, J.-W. Su, P.-J. Lu, J.-H. Wang, T.-W. Liu, S.-Y. Wu, R. Liu, Y.-C. Chou, Y.-L. Chung, W. Shih, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, N.-C. Lien, W.-C. Shih, Y. He, Qiang Li, Meng-Fan Chang, “A local computing cell and 6T SRAM-based computing-in-memory macro with 8-b MAC operation for edge AI chips,” IEEE Journal of Solid-State Circuits (JSSC), Sep. 2021.

4. Ruiqi Guo, Zhiheng Yue, Xin Si, T. Hu, H. Li, L. Tang, Y. Wang, L. Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin, “A 5.99-to-691.1 TOPS/W tensor-train in-memory-computing processor using bit-level-sparsity-based optimization and variable-precision quantization,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2021.

5. Sanfeng Zhang, Xiong Zhou, Chen Gao, Qiang Li, “An AC-coupled instrumentation amplifier achieving 110-dB CMRR at 50 Hz with chopped pseudoresistors and successive-approximation based capacitor trimming,” IEEE Journal of Solid-State Circuits (JSSC), Jan. 2021.
   

6. Zheng Zhu, Xiong Zhou, Yuheng Du, Yao Feng, Qiang Li, "A 14-bit 4-MS/s VCO-based SAR ADC with deep metastability facilitated mismatch calibration," IEEE Journal of Solid-State Circuits (JSSC), Jun. 2020.

7. Sanfeng Zhang, Chen Gao, Xiong Zhou, Qiang Li, “A 130dB CMRR instrumentation amplifier with common-mode replication,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2020.
   

8. Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Qiang Li, “A scalable 20GHz on-die power supply noise analyzer with compressed sensing,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2020. (ISSCC STGA Award)

9. Xin Si, Y.-N. Tu, W.-H. Huang, J.-W. Su, P.-J. Lu, J.-H. Wang, T.-W. Liu, S.-Y. Wu, R. Liu, Y.-C. Chou, Z. Zhang, S.-H. Sie, W.-C. Wei, Y.-C. Lo, T.-H. Wen, T.-H. Hsu, Y.-K. Chen, W. Shih, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, N.-C. Lien, W.-C. Shih, Y. He, Qiang Li, Meng-Fan Chang, “A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2020.

10. Xin Si, J.-J. Chen, Y.-N. Tu, W.-H. Huang, J.-H. Wang, Y.-C. Chiu, W.-C. Wei, S.-Y. Wu, X. Sun, R. Liu, S. Yu, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Qiang Li, Meng-Fan Chang, “A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors,” IEEE Journal of Solid-State Circuits (JSSC), Jan. 2020.

11. Lishan Lv, Xiong Zhou, Zhiliang Qiao, Qiang Li, "Inverter-based subthreshold amplifier techniques and their application in 0.3V ΔƩ-modulators," IEEE Journal of Solid-State Circuits (JSSC), May 2019.

12. Zhaoming Ding, Xiong Zhou, Qiang Li, "A 0.5–1.1V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator," IEEE Journal of Solid-State Circuits (JSSC), Apr. 2019. (VLSI invited submission)

13. Xin Si, Jia-Jing Chen, Y.-N. Tu, W.-H. Huang, J.-H. Wang, W.-C. Wei, S.-Y. Wu, X. Sun, R. Liu, S. Yu, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Qiang Li, Meng-Fan Chang, “A twin-8T SRAM computation-in-memory macro for multiple-bit CNN based machine learning,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2019.

14. Lishan Lv, Ankesh Jain, Xiong Zhou, Joachim Becker, Qiang Li, Maurits Ortmanns, "A 0.4V Gm-C proportional-integrator-based continuous-time ΔƩ modulator with 50kHz BW and 74.4dB SNDR," IEEE Journal of Solid-State Circuits (JSSC), Nov. 2018.

15. Xiaofei Ma, Yan Lu, R. Martins, Qiang Li, "A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS," International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018. (ISSCC STGA Award)

16. W.-S. Khwa, J.-J. Chen, J.-F. Li, Xin Si, E.-Y. Yang, X. Sun, R. Liu, P.-Y. Chen, Qiang Li, S. Yu, Meng-Fan Chang, “A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors,” International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018.

17. Qiang Li, Y. P. Zhang, "CMOS T/R switch design: towards ultra-wideband and higher frequency," IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 3, pp. 563-570, Mar. 2007.

18. 李强, 中国芯的ISSCC/JSSC之路, 华人芯片设计技术研讨会ICAC公众号 (ICAC Workshop) , May 31, 2020. [Online] Available: https://mp.weixin.qq.com/s/Xu05wKLz-zDCIilY9ewAAA.

selected only, last update: 2021/12/31