A 0.029-mm 2 17-fJ Conversion-Step Third-Order CT Delta Sigma ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer
- 所属单位：
UESTC
- 教研室：
CRFICS
- 发表刊物：
IEEE Journal of Solid-State Circuits
- 关键字：
Capacitors , Complexity theory , Noise shaping , Energy resolution , Robustness , Sun , Circuit stab
- 摘要：
This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converter (ADC) with a single operational transconductance amplifier (OTA). A 4-bit second-order fully passive noise-shaping (NS) successive-approximation-register (SAR) ADC is employed as the quantizer while inherently provides two additional NS orders. Fabricated in 40-nm CMOS, the prototype occupies 0.029 mm 2 of active area and consumes 1.16 mW of power when clocked at 500-MHz sampling frequency. The proposed CT ΔΣ ADC achieves a peak signal-to-noise-and-distortion ratio (S
- 论文类型：
应用研究
- 卷号：
54
- 期号：
2
- 页面范围：
428-440
- 是否译文：
否
