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A 32-Unit 240-GHz heterodyne receiver array in 65-nm CMOS with array-wide phase locking

Journal:Journal of Solid-State Circuits (JSSC)

All the Authors:Cheng Wang

First Author:Zhi Hu

Correspondence Author:Ruonan Han

Discipline:Engineering

Volume:54

Issue:5

Page Number:1216-1227

Translation or Not:no

Date of Publication:2019-05-01

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