A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking

2021-11-10 Hits:

Affiliation of Author(s):Massachusetts Institute of Technology (MIT)

Journal:IEEE Journal of Solid-State Circuits (JSSC)

Place of Publication:USA

Key Words:CMOS, compact electromagnetic design, heterodyne sub-terahertz receiver, high-density scalable array

Abstract:This paper reports a 32-unit phase-locked dense heterodyne receiver array at fRF = 240 GHz. To synthesize a large receiving aperture without large sidelobe response, this chip has the following two features. The first feature is the small size of the heterodyne receiver unit, which is only λ(fRF)/4 × λ(fRF)/2. It allows for the integration of two interleaved 4 × 4 arrays within a 1.2 mm2 die area for concurrent steering of two independent beams. Such unit compactness is enabled by the multi-functionality of the receiver structure, which simultaneously accomplishes local oscillator (LO) generat

Note:https://ieeexplore.ieee.org/document/8637931

All the Authors:Cheng Wang

First Author:Zhi Hu

Indexed by:Journal

Correspondence Author:Ruonan Han

Document Code:10.1109/JSSC.2019.2893231

Discipline:Engineering

Volume:54

Issue:5

Page Number:1216-1227

Translation or Not:no

Date of Publication:2019-05-01

Date of Publication:2019-05-01