A 94.4fsrms Cryogenic Sub-Sampling PLL in 4K for Quantum Computing Applications

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Affiliation of Author(s):University of Electronic Science and Technology of China (UESTC)

Journal:2024 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

Place of Publication:Chengdu, China

Key Words:SSPLL, PI, DTC, quantum interface

Abstract:This paper presents a fractional-N sub-sampling PLL (SSPLL) for cryogenic frequency source of in the quantum meas-urement and controller system. The proposed SSPLL adopts a 5-bit vector modulator (VM) based phase-interpolator (PI) and a 5-bit digital-to-time converter (DTC) for in-band phase noise sup-pression. According to the measured result, the SSPLL spans from 11.4GHz to 13.8GHz in 4K. When the SSPLL is divided by two, the output frequency is 6.3GHz. The measured RMS jitter is 94.37fs, the phase noise is -113.72dBc/Hz@100kHz, and the figure-of-the-merit (FoM) of -245.9dB is achieved.

Note:https://ieeexplore.ieee.org/document/10812563
Best student paper award (2nd prize)

All the Authors:Fang Shen,Xiong Fan

First Author:Shuting Peng

Indexed by:Conference

Correspondence Author:Jie Xu,Cheng Wang

Document Code:10.1109/RFIT60557.2024.10812563

Discipline:Engineering

First-Level Discipline:Electronic science and technology

Translation or Not:no

Date of Publication:2024-08-28

Date of Publication:2024-08-28