阮爱武
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Block diagram of an in-house developed SOC HW/SW Co-Verification System
First generation co-verification system
Second generation co-verification system
Third generation co-verification system
A hierarchy communication channel in transaction-level HW/SW co-emulation system is proposed, including physical layer, transport layer, transaction layer and application layer.
A communication protocol of transport layer is self-defined to implement multiplexing of logic channels.
A stream-mode based HW/SW co-emulation technique is proposed to address communication bottleneck when data exchanging is required between software side nd hardware side in an HW/SW co-verification system.
HW/SW co-verification based system for FPGA test and diagnosis:
Block diagram of an in-house developed system for FPGA test and diagnosis
A flow chart of automatic configuration generation and test
Methodology for FPGA test and diagnosis
We have investigated algorithms for FPGA test and diagnosis covering all FPGA resources such as, configurable logic blocks (CLBs), interconnect resources (IRs), input/output blocks (IOBs), wide edge decoder, et al with minimum configuration numbers. Not only multiple faults in FPGA can be detected, but location and type of the multiple faults can also be determined by the FPGA test system and associated test schemes. 100% fault coverage can be achieved in experiment. Optimized algorithm for testing and diagnosing all FPGA resources simultaneously is now under investigation.
IOB modeling by Graph Theory
CLB modeling by Graph Theory
Fault detection and diagnosis of the programmable Interconnect Resources (IRs) poses challenge for FPGA testing，especially when it is necessary to decide fault type and fault location accurately. A fault mapping algorithm for fault detection and diagnosis of the IRs by mapping faults of IRs to outputs of the corresponding LUTs is presented. The algorithm is applicable to integrated circuits like FPGA consisting of many repeatable units, as well as FPGA online testing. In the FPGA online testing, the minimum testing numbers are independent of FPGA size and are only relevant to the proportion between resources occupied by configured user circuit and FPGA size.
Three test configurations for IRs based on Repeatable Unit
Proposed array of TCLD
Defect and fault tolerant computing for FPGA (2010 ～ )
(3) The third generation verification technology based SOC debugging (2010 ～ )Co-verification technologies are characterized by two inherently conflicting issues: signal observability and simulation performance. To overcome these limitations, we proposed a run-time RTL debugging methodology for FPGA-based co-simulation as well as debugging methodology for a FPGA emulator with testbench synthesis engine. The first method provides internal nodes probing on an event-driven co-simulation platform and achieves full observability for DUT with better simulation performance. In the second method, the proposed testbench synthesis engine is built by hardware constructs in terms of Verilog IEEE Simulation Model to correspond with the testbench. Internal nodes are hardware-wired to DUT top-level during compilation, then sampled continuously by a sample logic into on-chip storage device (e.g. Block RAM, SDRAM and etc). Thus better observability can be achieved without stopping of DUT clock.
A run-time RTL debugging methodology for FPGA-based co-simulation
Design flow for co-simulation based debugging
Debugging methodology for a FPGA emulator with testbench synthesis engine
A event driven testbench synthesis engine called BeEmu (Behavior-Level Emulator) to translate the behavioral testbench into synthesizable one for FPGA emulation
Block diagram of behavioral emulator with debug system
整个版图采用0.6um PWELL Single Poly Double Metals CMOS工艺，全定制设计方式，包含近30万个MOS管，面积达17×17mm²，已经接近6英寸片的光刻曝光极限。
FRAM is regarded as a promising product for the future memory because of the merits of high speed, low cost, low power-consumption, low voltage supply and excellent radiation hardness.
