6-1 A 230GHz, 128-unit Zero-IF Phased Array RX utilizing 1-D SSPLL and DTC Phase Shifter

2026-06-27 Hits:

Affiliation of Author(s):University of Electronic Science and Technology of China (UESTC)

Teaching and Research Group:Integrated Physics Group (IPG)

Journal:2026 IEEE Custom Integrated Circuits Conference (CICC)

Place of Publication:Seattle, WA, USA

Abstract:This work presents a 230-GHz, 128-unit, λ/2-spaced planar phased array receiver (RX) utilizing a 1-D SSPLL and a DTC phase shifter. To construct a large-scale phased array system with a precise λ/2 antenna spacing above 200 GHz, this work addresses three key challenges. First, to achieve cross-chip synchronization among multiple chips, a 1-D SSPLL is proposed to enable arbitrary local oscillator (LO) synchronization for each tile while reducing clock jitter, achieving a measured ultra-low jitter of 44 fs. Second, to reduce the loss of LO driving power while maintaining precise beam steering, a

Note:https://ieeexplore.ieee.org/document/11509561

All the Authors:Yan Li,Jun Yuan,Zhiang Wang,Lihan Wang,Yinian Feng,Zheng Wang,Zhi Chen,Bo Zhang

First Author:Xiangao Meng

Indexed by:Conference

Correspondence Author:Cheng Wang

Document Code:10.1109/CICC65509.2026.11509561

Discipline:Engineering

First-Level Discipline:Electronic science and technology

Translation or Not:no

Date of Publication:2026-04-19

Date of Publication:2026-04-19