C4.1 A 209~245GHz CMOS Spectroscopic Transmitter with DTC-Based 4FSK Baseline Elimination and Phase-Offset Calibrated SSPLL for Chip-Scale Molecular Clocks

2026-06-27 Hits:

Affiliation of Author(s):University of Electronic Science and Technology of China (UESTC)

Teaching and Research Group:Integrated Physics Group (IPG)

Journal:2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI)

Place of Publication:Honolulu, Hawaii, US

Key Words:chip-scale molecular clock, CMOS spectrometer, 4FSK modulation, DTC, phase offset calibration

Abstract:This paper presents a CMOS spectroscopic transmitter probing the 231.061GHz rotational spectra of OCS gas molecules for chip-scale molecular clocks (CSMC). It adopts 4FSK modulation through a DTC FSK modulator to mitigate the baseline tilting of gas cell with negligible SNR penalty. A 104.4~122.4GHz integer-N sub-sampling PLL (SSPLL, N=36) reduces the phase noise (PN) for high SNR. Phase offset calibration ensures robust locking of SSPLL under PVT variation. A 5.8~6.8GHz fractional-N sampling PLL (SPLL) drives the SSPLL. Fabricated on 65-nm bulk CMOS, it achieves a measured PN of −79.2dBc/Hz.

Note:https://www.vlsisymposium.org/

All the Authors:Xiao Luo,Xinyang Chen,Chang Liu

First Author:Geyu Qiang

Indexed by:Conference

Correspondence Author:Cheng Wang

Discipline:Engineering

First-Level Discipline:Electronic science and technology

Translation or Not:no

Date of Publication:2026-06-25

Date of Publication:2026-06-25