A Cryo-CMOS 20-Bit R-2R Ladder DAC for the Manipulation of Silicon and Carbon Nanotube Qubits

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Affiliation of Author(s):University of Electronic Science and Technology of China (UESTC)

Teaching and Research Group:Integrated Physics Group (IPG)

Journal:2023 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP)

Place of Publication:Chengdu, China

Key Words:Cryo-CMOS, digital-to-analog converter, R-2R ladder, silicon Qubit, carbon nanotube Qubit

Abstract:This paper presents a 65nm cryogenic CMOS, high-precision (20-bit), low noise, low power digital-to-analog converter (DAC) designed for the manipulation of silicon and carbon nanotube qubits. The DAC adopts a R-2R ladder architecture with built-in calibration. The lower 14-bits of DAC adopt a binary weighted R-2R ladder, while the higher 6-bits adopt a thermometer-coded equally-weighted resistor network. It uses a 6R-3R calibration scheme to improve the linearity. Measured under 6K, the DAC achieves a differential linearity (DNL) ≤+/−3LSB, an output noise spectral density of 3.374nV/√Hz@10kHz

Note:https://ieeexplore.ieee.org/document/10381481

All the Authors:Yan Xu

First Author:Yingjie Li

Indexed by:Conference

Correspondence Author:Cheng Wang

Document Code:10.1109/IMWS-AMP57814.2023.10381481

Discipline:Engineering

First-Level Discipline:Electronic science and technology

Translation or Not:no

Date of Publication:2023-11-13

Date of Publication:2023-11-13