Adhesive bonding is one of the most frequently used techniques for die attachment in microelectronics and microsystem packaging. The thermal stress induced by the mismatch of coefficients of thermal expansion(CTE) under temperature change is a key factor to the packaging reliability. An analytical prediction model is proposed to evaluate the interfacial thermal stress of tri-layer packaging with void in
adhesive rather than an ideal model which is broadly adopted in current publications. The proposed method focuses on the stresses at the voids and chip edges that always possesses the maximum stress resulting in the delamination and dislocation failure. The prediction results showed a good agreement with
numerical simulation and exhibited a more accurate evaluation of interfacial shearing stresses at the edges of void and tri-layer structure than Suhir’s method. The study indicated that the maximum shearing stress occurred at the structure edges of interface of adhesive and smaller CTE material while the maximum stress in interface of adhesive and bigger CTE layer appeared at the edges of voids. The shearing stresses in the areas far from void in void model are almost the same as the model without voids. Both conclusions provided a useful guideline to the design of packaging reliability of micro systems.