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所属单位：University of Electronic Science and Technology of China (UESTC)

教研室：Integrated Physics Group (IPG)

发表刊物：2026 IEEE Custom Integrated Circuits Conference (CICC)

刊物所在地：Seattle, WA, USA

摘要：This work presents a 230-GHz, 128-unit, λ/2-spaced planar phased array receiver (RX) utilizing a 1-D SSPLL and a DTC phase shifter. To construct a large-scale phased array system with a precise λ/2 antenna spacing above 200 GHz, this work addresses three key challenges. First, to achieve cross-chip synchronization among multiple chips, a 1-D SSPLL is proposed to enable arbitrary local oscillator (LO) synchronization for each tile while reducing clock jitter, achieving a measured ultra-low jitter of 44 fs. Second, to reduce the loss of LO driving power while maintaining precise beam steering, a

备注：https://ieeexplore.ieee.org/document/11509561

全部作者：Yan Li,Jun Yuan,Zhiang Wang,Lihan Wang,Yinian Feng,Zheng Wang,Zhi Chen,Bo Zhang

第一作者：Xiangao Meng

论文类型：会议

通讯作者：Cheng Wang

论文编号：10.1109/CICC65509.2026.11509561

学科门类：工学

一级学科：电子科学与技术

是否译文：否

发表时间：2026-04-19