Cheng Wang, Professor at University of Electronic Science and Technology of China, Vice Dean of Sichuan Quantum Science and Technology Institute.

1. Biography

May 2026 – Present, Vice Dean, Sichuan Quantum Science and Technology Institute

Jan 2022 – Present, Professor, University of Electronic Science and Technology of China (UESTC)

Mar 2021 – Dec 2021, Research Fellow, University of Electronic Science and Technology of China (UESTC)

Nov 2019 – Jan 2021, Research Scientist, Analog Devices, Inc. (ADI), USA

Aug 2015 – Feb 2020, Ph.D., Massachusetts Institute of Technology (MIT), USA

Jun 2011 – Jul 2015, Assistant Researcher, China Academy of Engineering Physics (CAEP)

Oct 2008 – Jun 2011, Master of Science, China Academy of Engineering Physics (CAEP)

Aug 2004 – Jul 2008, Bachelor of Engineering, Tsinghua University (THU)

Find personal resume at: Resume of Cheng Wang

2. Research Fields

Prof. Cheng Wang founded the Integrated Physics Group (IPG), focusing on the interdisciplinary frontier of silicon-based integrated circuits and applied physics. To date, the group has published more than 50 high-impact papers in the circuit field, including:

Journals:

1× Nature Electronics;

8× IEEE Journal of Solid-State Circuits (JSSC);

6× IEEE Transactions on Microwave Theory and Techniques (TMTT);

3× IEEE Transactions on Terahertz Science and Technology (TTST);

1× IEEE Transaction on Biomedical Circuits and Systems (TBioCAS);

1× IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I);

2× IEEE Microwave and Wireless Technology Letters (MWTL).

Conferences:

6× International Solid-State Circuits Conference (ISSCC);

2× Symposium on VLSI Technology and Circuits (VLSI);

1× Custom Integrated Circuits Conference (CICC);

4× Radio Frequency Integrated Circuits Symposium (RFIC);

4× European Solid-State Electronics Research Conference (ESSERC);

2× International Electron Devices Meeting (IEDM);

1× Asian Solid-State Circuits Conference (ASSCC).

For the full list of publications, please refer to: Papers and Slides and Google Scholar.

2.1 Cryogenic Silicon Integrated Circuits for Quantum Computing (Cryo-CMOS)

Xiling: 65nm cryo-CMOS chip realizes manipulation of silicon single-electron transistors (SETs) at 60 mK, published in ISSCC 2025 and JSSC 2026, and selected as a Research Highlight by Nature Electronics.

PAEMS: precise and adaptive error model for superconducting qubits, released on arXiv 2026.

Emei: 28nm cryo-CMOS Frequency-Division Multiplexing Chip for superconducting quantum state discrimination. It adopts a mixer-first architecture (w/o low-noise amplifiers, LNAs), achieving  >95% qubit readout fidelity and 17K noise temp., published in TMTT 2026 .

4K cryo-CMOS low-noise amplifiers (LNA) achieve state-of-the-art noise performance, published at RFIC 2026 and ESSERC 2026.

A cryo-CMOS readout chip based on degenerate parametric amplification (DPA) was proposed, published JSSC 2024 (Invited) and ASSCC 2023.

A 4.2 K cryo-CMOS voltage-controlled oscillator (VCO) achieves a record figure-of-merit (FoM) of 202.3 dBc/Hz, published at ISSCC 2023.

2.2 Chip-Scale Molecular Clocks (CSMC)

The 1st chip-scale molecular clock (CSMC) was featured as the cover page of Nature Electronics (2018), receiving wide media coverage including MIT News. Further details are revealed in JSSC 2019 (Invited) and VLSI 2018.

Lamb-dip in a FQ cavity to further boost the Q factor of gas rotational spectra of OCS for CSMC, published on TMTT 2025 and selected as a TMTT Featured Article.

The 4th-gen. CSMC based on 4FSK DTC modulator and cascaded PLL was presented at VLSI 2026 with on-site live demonstration.

A  mixed-signal baseband processing chip for the 4th-gen. CSMC will be published at ESSERC 2026.

The 3rd-gen. CSMC adopting dual-loop locking was published at RFIC 2022.

The 2nd-gen. CSMC with high-order dispersion curve locking was presented at ISSCC 2020 with on-site live demo, and published in JSSC 2021.  

A dual-frequency-comb chip for gas rotational spectroscopy detection was published at ISSCC 2017 , JSSC 2017 (Invited, on circuit), and TBioCAS 2018 (Invited, on spectroscopy).

2.3 Large-Scale Scalable Terahertz Phased Arrays

A 230 GHz, 128-element phased-array receiver (RX) delivers the largest array size and lowest EINF, published at CICC 2026.

300–320 GHz, 32-element phased-array transmitter (TX) and receiver (RX) set benchmarks in array scale and overall performance, published at ESSERC 2026 TX and ESSERC 2026 RX, respectively.

A 230 GHz, 32-element phased-array transmitter (TX) achieves a record high EIRP, published in TMTT 2026 and selected as a TMTT Featured Article.

A D-band (140 GHz), 64-element phased-array transmitter (TX) demonstrated a scalable array configuration with half-wavelength spacing for the first time, published at ISSCC 2024  and in TMTT 2025, and selected as an ISSCC Research Highlight.

3. Honors & Awards

2024,  Sichuan May 4th Youth Medal.

2023,  35 Innovators Under 35 (China), MIT Technology Review.

2020,  IEEE SSCS Predoctoral Achievement Award, IEEE SSCS Society.

2019,  MTL Doctoral Dissertation Seminar, MIT Microsystems Technology Laboratories (2 recipients annually).

2018,  Chinese Government Award for Outstanding Self-Financed Students Abroad, China Scholarship Council (CSC).

4. Graduate Advising (Updated on June 30th, 2026)

10 PhD Students, 7 Co-advised PhD Students

        -- 4 PhD students have graduated since 2024, including co-advised students.

16 Master Students, 16 Co-advised Master Students

        -- 15 master students have graduated since 2023, including co-advised students.

12 Advised Students Admitted to Overseas Graduate Programs

        -- PhDs: MIT ×3, UT Austin ×1, WSU ×1, Rice ×1

        -- Masters: Cornell ×1, UT Austin ×1, Georgia Tech ×1, UCLA ×1, HKUST ×1, CityU ×1